1. Field of the Invention
The present invention relates to a sense amplifier circuit of a semiconductor memory device, and more particularly to a CMOS cross-coupled sense amplifier circuit that detects and amplifies data of a memory cell.
2. Description of the Related Art
Due to technological trends in the field of semiconductors including, increased density, tighter design rules and lower supply voltages to drive memory devices, a sense amplifier that can detect and amplify voltage of memory cells has been developed to perform high speed operations but with low power consumption. A representative structure of a sense amplifier that performs high-speed operations but consumes low power is a cross-coupled device. Cross-coupled sense amplifiers have been successfully utilized to detect and amplify the voltage of memory cells in a static RAM (SRAM). The structure of such a CMOS cross-coupled sense amplifier is illustrated in FIG. 1.
FIG. 1 is an illustration of a prior art CMOS cross-coupled sense amplifier.
FIG. 2 is a graph showing currents between drain and source (Ids) according to voltage between drain and source (Vds) and voltage between gate and source (Vgs) in a conventional N-type MOS transistor. Plots shown with a solid line and a dotted line designate the current Ids for a drain and source, respectively, in a transistor whose threshold voltage mismatches are indicated as xe2x88x92xcex94V and +xcex94V, respectively.
Now, operations of the prior art CMOS cross-coupled sense amplifier circuit will be briefly described with reference to FIGS. 1 and 2.
As shown in FIG. 1, the CMOS cross-coupled sense amplifier circuit includes a PMOS transistor 12 and an NMOS transistor 14 connected in a series between supply voltage Vdd and a first internal node IN1. The gates of PMOS transistor 12 and NMOS transistor 14 are connected to a second output node ON2 for inverting a signal input to the gates outputting the signal to a first output node ON1. PMOS transistor 16 and NMOS transistor 18 are connected in series between supply voltage Vdd and a second internal node IN2. The gates of PMOS transistor 16 and NMOS transistor 18 are connected to a first output node ON1 for inverting a signal input to the gates and outputting the signal to a second output node ON2. A first equalization transistor 20 is connected between the first and second internal nodes, IN1 and IN2, for equalizing electric potential of the internal nodes, IN1 and IN2 in response to a control signal, CS. The control signal, CS, is input from outside at a pre-charged level. A first input transistor 22 is connected between a pull-down node PN and the first internal node IN1 for inputting voltage of a bit line BL to a gate. A second input transistor is connected between the pull-down node PN and the second internal node IN2 for inputting voltage of a bit line BLB to its gate. A driving transistor 26 is connected between the pull-down node PN and ground for pulling down the electric potential of the pull-down node PN to a ground level in response to a control signal, CS, input to its gate is at a driving level. BLB is the complement bit line of bit line BL.
Reference numerals 28 and 30 are pre-charge transistors connected between supply voltage Vdd and the first output node ON1, and between supply voltage Vdd and the second output node ON2, respectively. The pre-charge transistors 28 and 30 pre-charge the first and second output nodes ON1 and ON2 to the level of supply voltage, Vdd, by switching when the control signal, CS, input to gates of the transistors is at the pre-charge level. In addition, reference numeral 32 is a second equalization transistor. The second equalization transistor 32 equalizes the electric potential of the two output nodes ON1 and ON2, in response to an input of a pre-charged level of a control signal CS. As shown in FIG. 1, the first and second input transistors 22 and 24, and the driving transistor 26 are NMOS transistors. The first and second equalization transistors 20 and 32, and pre-charge transistors 28 and 30 are PMOS transistors.
Operations of the CMOS cross-coupled sense amplifier circuit thus constructed will be described briefly. A control signal, CS, to drive the sense amplifier, maintains an initial low level of logic but turns into a xe2x80x9chighxe2x80x9d level of logic for a predetermined period of time when a semiconductor memory device is activated. For example, when a low address strobe signal is activated to allow data input and output to memory cells (not shown). Accordingly, if the control signal, CS, is low and input at the pre-charge level, the pre-charge transistors 28 and 30, and the first and second equalization transistors, 20 and 26, are all xe2x80x9cturned onxe2x80x9d. At the pre-charge mode as such, the first and second output nodes, ON1 and ON2, are pre-charged to the level of supply voltage, xe2x80x9cVddxe2x80x9d, and, equalized by the second equalization transistor to get ready to detect and amplify the electric potential of bit lines BL/BLB. The electric potential of the first and second internal nodes, IN1 and IN2, is equalized by turning on the first equalization transistor 20. After completion of pre-charge and equalization operations, bit lines, BL and BLB, are to be maintained at the same electric potential.
After a memory cell (not shown) is selected to develop its electric potential, it is transferred to bit lines BL and BLB, connected to the related memory cell and provided to the NMOS transistors 22 and 24. At this time, when the control signal, CS, is activated to its high level from its low level of logic, the sense amplifier, shown in FIG. 1, is driven. The pre-charge transistors 28 and 30, and the first and second equalization transistors, 20 and 32, are turned off, and the driving transistor 26 is turned on to pull down the electric potential of the pull-down node PN to ground. If the driving transistor 26 is turned on, the sense amplifier circuit, shown in FIG. 1, amplifies a voltage difference developed in the electric potential from the memory cell and outputs it to the first and second output nodes, ON1 and ON2.
For example, if a voltage offset loaded at bit lines BL and BLB, exceeds a predetermined level of voltage, e.g., if the voltage offset of the bit lines BL and BLB develop into (+)/(xe2x88x92), the voltage of the first and second internal nodes, IN1 and IN2, increases in different directions by operations of the first and second input transistors, 22 and 24. The voltage of the first and second internal nodes, IN1 and IN2, is amplified by the four transistors 12, 13, 14 and 16, connected in the latch type between the first and second internal nodes, IN1 and IN2, and then, output to the first and second output nodes, ON1 and ON2, as levels of logic, xe2x80x9clow, highxe2x80x9d or xe2x80x9chigh, lowxe2x80x9d.
The conventional sense amplifier circuit shown in FIG. 1 performs its normal operations if the voltage offset of bit lines BL and BLB become greater than a predetermined level, but does not perform its normal operations if the voltage offset of bit lines BL and BLB becomes smaller than a predetermined level. A minimum voltage offset of the bit lines BL and BLB that can operate the sense amplifier circuit is defined as a voltage margin of a sense amplifier. As the minimum voltage offset as such becomes smaller, the sense margin of a sense amplifier is considered favorable. As the minimum voltage offset becomes greater, the sense margin of a sense amplifier is considered poor.
However, the sense amplifier shown in FIG. 1 has a large number of inter-related transistors, so it may not operate with an input level of voltage offset because of a mismatch among transistors. The mismatch includes a mismatch in the thickness or length of channels, in capacitance or in threshold voltage, thereby transistors behave differently with variations in the manufacturing process. In other words, a sense amplifier may have a worse sense margin than another type of a sense amplifier. If a mismatch that occurred in the manufacturing processes results in a mismatch in the threshold voltage of transistors in the sense amplifier constructed as shown in FIG. 1. The voltage margin between bit lines BL and BLB should be sufficiently great, e.g., greater level of voltage than usual.
Therefore, if the sense amplifier circuit shown in FIG. 1 does not have a sufficiently great voltage margin between bit lines BL and BLB, it may falsely operate or may not operate due to a mismatch in transistors.
The aforementioned problem will be described in more detail. There may be false operations due to a mismatch that occurred in transistors forming a CMOS cross-coupled sense amplifier. For example, if no mismatch of transistors occurs under the supposed conditions that the voltage levels of bit lines BL and BLB are V+xcex94V and Vxe2x88x92xcex94V and the voltage offset of the bit lines BL and BLB is a positive (+) voltage, the sense amplifier, shown in FIG. 1, will perform normal operations. Thus, the level of voltage. Further, xe2x80x9c0Vxe2x80x9d will be output to the first output node ON1 and Vdd will be supplied to the second output node ON2.
However, supposing that there is a severe mismatch of transistors forming the sense amplifier shown in FIG. 1, the sense amplifier shown in FIG. 1 cannot generate a correct amplifying signal. The level of voltage at the first output node ON1 becomes the supply voltage Vdd, and of the voltage at the second output node ON2 becomes xe2x80x9c0Vxe2x80x9d. Even if there may be a variety of reasons causing the mismatch of transistors as described above, we will illustrate the mismatch problem by describing one that occurred in the fabricating processes for convenience.
In the sense amplifier shown in FIG. 1, the absolute value of the threshold voltage at the PMOS transistor 16 and NMOS transistors 14 and 22 should be raised by xcex94Vth to prevent the output voltage at the first output node ON1 from being xe2x80x9c0xe2x80x9d. The absolute value of the threshold voltage at the PMOS transistor 12 and NMOS transistors 18, 24 should be lowered by xcex94Vth to prevent the output voltage of the second output node ON2 from becoming xe2x80x9cVddxe2x80x9d.
If a mismatch in the threshold voltage of transistors is caused by problems related to the fabricating processes, an undesired level of output voltage may be obtained. Due to the above-mentioned mismatch in the threshold voltage of the transistors, if the difference in the input voltage of the sense amplifier shown in FIG. 1, e.g., the voltage offset of 2 xcex94Vth, is not large enough to overcome mismatches in voltage between the first and second internal nodes, IN1 and IN2, and between the first and second output nodes, ON1 and ON2, an undesired level of voltage of output voltage is obtained. The mismatches in voltage between the first and second internal nodes, IN1 and IN2, and between the first and second output nodes, ON1 and ON2, may be caused by current Ids between drain and source of the NMOS transistor 14 or 18. The phases of an output voltage are xe2x80x9cVddxe2x80x9d and xe2x80x9c0xe2x80x9d at the first and second output nodes, ON1 and ON2, respectively. A further detailed description will be made about it below.
In case of transistors having voltage Vgs between gate and source and voltage Vds between drain and source, the current Ids of the NMOS transistor having (+)xcex94Vth becomes greater than that of the NMOS transistor having (xe2x88x92)xcex94Vth. As shown in FIG. 2, in case of transistors having identical Vds, Vgs, there becomes a difference in the current Ids between drain and source by xcex94Ids due to (xe2x88x92)xcex94Vth and (+)xcex94Vth.
If the aforementioned concept can be applied to the transistors at an initial operational stage of the sense amplifier, the following description can be made about a worst mismatch in the CMOS cross-coupled sense amplifier shown FIG. 1. The threshold voltage of the NMOS transistor 22 that inputs voltage of the bit line BL to the gate is greater than that of the NMOS transistor 24, which inputs voltage of the bit line BLB to the gate, so that the current Ids of the NMOS transistor 24 becomes greater than that of the NMOS transistor 22. Further, as the threshold voltage of the NMOS transistor 14 becomes greater than that of the NMOS transistor 18 in CMOS latch, the current Ids of the NMOS transistor 18 becomes greater than that of the NMOS transistor 14. The voltage Vds between drain and source and the voltage Vgs between gate and source of the PMOS transistors 12 and 16, are very close to xe2x80x9c0Vxe2x80x9d, so that there may be no difference in the current Ids of the two PMOS transistors 12 and 16.
As described above, the current Ids of respective transistors flows in undesired directions due to a mismatch in the threshold voltage of the transistors forming the sense amplifier shown in FIG. 1.
Therefore, a need exists for a sense amplifier having a minimum voltage offset greater than when there is no mismatch.
It is an object of the present invention to provide a sense amplifier circuit that efficiently senses and amplifies the level of an electric potential developed signal even if a mismatch occurs in transistors.
It is another object of the present invention to provide a structure of a CMOS cross-coupled sense amplifier circuit having a superior sense margin.
It is a further another object of the present invention to provide a structure of a cross-coupled sense amplifier circuit that detects and amplifies the electric potential of bit lines having a superior sense margin even if a mismatch occurs in transistors of a chip due to conditions of fabricating processes.
In order to accomplish the aforementioned object of the present invention, there is provided a sense amplifier circuit comprising:
a first inverter having PMOS and NMOS transistors with respective drains being connected to a first output node and respective sources being connected to a supply voltage, and a first node connected to respective gates commonly connected to a second output node;
a second inverter having PMOS and NMOS transistors with respective drains being connected to a second output node and respective sources being connected to supply voltage, and a second node connected to respective gates commonly connected to a first output node;
first and second input transistors, with respective channels connected between the first node and a pull-down node and between the second node and the pull-down node, respectively, for pulling the first and second nodes to an electric potential of the pull-down node according to an electric potential of a bit line and complement bit line connected to respective gates of the first and second input transistors;
a driving transistor for pulling down the pull-down node to ground in response to activation of a predetermined level of a control signal; and
mismatch control transistors respectively connected between the drain and source of the NMOS transistors in the first and second inverters, for eliminating differences in voltage between the first output node and the first node, and between the second output node and the second node, in response to non-activation of the control signal.
It is preferable that the sense amplifier circuit of the present invention has an equalization transistor between the first and second nodes for equalizing the electric potential of the first and second nodes in response to non-activation of the control signal.
It is also preferable that the sense amplifier circuit has pre-charge transistors for pre-charging the potential of the first and second output nodes to a level of supply voltage in response to non-activation of the control signal.
Also, the sense amplifier circuit includes a second equalization transistor connected between the first and second output nodes for equalizing the electric potential of the first and second output nodes to an identical level thereof in response to non-activation of the control signal.
According to an embodiment of the present invention, a method is provided for compensating for a difference between two or more like transistors of a sense amplifier. The method includes equalizing the electric potential between a first node and a second node in response to non-activation of a control signal, wherein at least a first equalization transistor is connected between the first and the second nodes. The method further includes pre-charging the electric potential of a first output node and a second output node to a level of supply voltage in response to non-activation of the control signal, wherein a first and a second pre-charge transistors are implemented with the control signal input at the respective pre-charge transistor gates. The method equalizes the electric potential of the first output node and the second output node in response to non-activation of the control signal, wherein at least a second equalization transistor is connected between the first and the second output nodes.
The method further includes equalizing the electric potential of the first node and the second node in response to the control signal at a pre-charge level.
The method pre-charges the electric potential of the first output node and the second output node to a level of a supply voltage in response to the control signal at a pre-charge level.
The method also equalizes the electric potential of the first output node and the second output node in response to the control signal at a pre-charge level.
The difference can be one or more of a difference in thickness of channels, in length of channels, in capacitance, and in threshold.